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M52790SP/FP
AV Switch with I2C Bus Control
REJ03F0187-0200 Rev.2.00 Sep 14, 2006
Description
The M52790 is AV switch semiconductor integrated circuit with I2C bus control. This IC contains 2-channels of 4-input audio switches and 2-channels of 4-input video switches. Each channel can be controlled independently. The video switches contain amplifiers can be controlled a gain of output 0 dB or 6 dB.
Features
* * * * Video and stereo sound switches in one package Wide frequency range (video switch): DC to 20 MHz High separation (video switch): Crosstalk -60 dB (Typ) at 1 MHz Two types of packages are provided: SDIP with a lead pitch of 1.778 mm (M52790SP); and SSOP with a lead pitch of 0.8 mm (M52790FP).
Application
Video equipment
Recommended Operating Condition
Supply voltage: Rated supply voltage: 4.7 V to 9.3 V 5 V, 9 V
Maximum output current: 63 mA (at 9 V)
Rev.2.00 Sep 14, 2006 page 1 of 13
M52790SP/FP
Block Diagram
VCC
TUNER IN
+
1 36 2 7
S
V-SW1 0/6 dB
VIDEO 2 IN
+
VIDEO 3 IN
+
31 C IN 34
S
V-SW2 N Y-SW1 0/6 dB 0/6 dB
V 1 OUT Y/C Sepa.
VIDEO 4 IN
+
12
Y IN 32 27 Y 1 OUT
Y 2 IN
+
6 11 16
Y 3 IN
+
Y 4 IN
+
22
Y-SW2 0/6 dB
Y 2 OUT V 2 OUT C 1 OUT
26 C 2 IN C 3 IN C 4 IN 4 9 14
N 0/6 dB
29
C-SW1 0/6 dB
24
C-SW2
C 2 OUT
Rch T IN
+
33 5 10 15
R-SW1
Rch 2 IN
+
R-MODE1
R M L
0 dB
Rch 3 IN
+
28
Rch 1 OUT
Rch 4 IN
+
R-MODE2
R
0 dB
Lch T IN
+
R-SW2
M L
23
Rch 2 OUT
35 3 8 13
L-SW1
Lch 2 IN
+
L-MODE1
L M R
0 dB
Lch 3 IN
+
30
Lch 1 OUT
Lch 4 IN
+
L-MODE2
L
0 dB
L-SW2
M R
25 18 17
Lch 2 OUT SDA SCL
BIAS 21 BIAS I2C Control
+
19 GND
20 CHIP SELECT
Rev.2.00 Sep 14, 2006 page 2 of 13
M52790SP/FP
Pin Arrangement
M52790SP
VCC VIDEO 2 IN Lch 2 IN C 2 IN Rch 2 IN Y 2 IN VIDEO 3 IN Lch 3 IN C 3 IN
1 2 3 4 5 6 7 8 9 36 TUNER IN 35 Lch T IN 34 C IN 33 Rch T IN 32 Y IN 31 V 1 OUT 30 Lch 1 OUT 29 C 1 OUT 28 Rch 1 OUT 27 Y 1 OUT 26 V 2 OUT 25 Lch 2 OUT 24 C 2 OUT 23 Rch 2 OUT 22 Y 2 OUT 21 BIAS 20 CHIP SELECT 19 GND
M52790FP
VCC VIDEO 2 IN Lch 2 IN C 2 IN Rch 2 IN Y 2 IN VIDEO 3 IN Lch 3 IN C 3 IN
1 2 3 4 5 6 7 8 9 36 TUNER IN 35 Lch T IN 34 C IN 33 Rch T IN 32 Y IN 31 V 1 OUT 30 Lch 1 OUT 29 C 1 OUT 28 Rch 1 OUT 27 Y 1 OUT 26 V 2 OUT 25 Lch 2 OUT 24 C 2 OUT 23 Rch 2 OUT 22 Y 2 OUT 21 BIAS 20 CHIP SELECT 19 GND
Rch 3 IN 10 Y 3 IN 11 VIDEO 4 IN 12 Lch 4 IN 13 C 4 IN 14 Rch 4 IN 15 Y 4 IN 16 SCL 17 SDA 18
Rch 3 IN 10 Y 3 IN 11 VIDEO 4 IN 12 Lch 4 IN 13 C 4 IN 14 Rch 4 IN 15 Y 4 IN 16 SCL 17 SDA 18
(Top view) Outline: 36P4E Lead pitch: 1.778 mm
(Top view) Outline: PRSP0036GA-B (36P2R-D) Lead pitch: 0.8 mm
Rev.2.00 Sep 14, 2006 page 3 of 13
M52790SP/FP
Pin Description
Pin No. 1 2 6 7 11 12 16 32 36 3 5 8 10 13 15 33 35 4 9 14 34 Name VCC VIDEO 2 IN Y 2 IN VIDEO 3 IN Y 3 IN VIDEO 4 IN Y 4 IN Y IN TUNER IN Lch 2 IN Rch 2 IN Lch 3 IN Rch 3 IN Lch 4 IN Rch 4 IN Rch T IN Lch T IN C 2 IN C 3 IN C 4 IN C IN Peripheral Circuit Pins --
40 k
DC Voltage (V) 9V 3.6 V
Remarks 5 to 9 V Clamp in
29.6 k
4.7 V
30 k
29.6 k
4.7 V
20 k
17
SCL
VIL max = 1.5 V VIH min = 3.0 V
18
SDA
VIL max = 1.5 V VIH min = 3.0 V VOL max = 0.4 V
At lin = 3 mA
19 20
GND CHIP SELECT
--
70 k 30 k
-- SLAVE ADDRESS 0 to 1.5 V: 90H 2.5 to VCC: 92H OPEN: 90H
Rev.2.00 Sep 14, 2006 page 4 of 13
M52790SP/FP
Pin No. 21
Name BIAS
Peripheral Circuit Pins
17.1 k 29.6 k
DC Voltage (V) 4.2 V
Remarks
13.9 k
30 k
22 26 27 31
Y 2 OUT V 2 OUT Y 1 OUT V 1 OUT
SYNC CHIP DC = 2.9 V
5k
5k
24 29
C 2 OUT C 1 OUT
4.0 V
5k
5k
23 25 28 30
Rch 2 OUT Lch 2 OUT Rch 1 OUT Lch 1 OUT
4.0 V
1.5 k
1.5 k
Rev.2.00 Sep 14, 2006 page 5 of 13
1.5 k
M52790SP/FP
I2C Bus
I2C Bus (Inter IC Bus) is multi master bus system developed by PHILIPS. Two wires (SDA-serial data, SCL-serial clock) realize functions of start, stop, transferring data, synchronization and arbitration. The output stages of device connected to the bus must have an open drain or open collector in order to perform the wired-AND function.
SDA A MSB SCL S 1 2 3 4 5 6 7 8 9 1 2 9 P LSB MSB LSB A
Note:
S: Start condition, a high to low transition of the SDA line while SCL is high P: Stop condition, a low to high transition of the SDA line while SCL is high A: Acknowledge
Every byte put on the SDA line must be 8-bits long. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first. The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW.
Control
This IC controls 2-channel switches with 2-byte data (DATA1 and DATA2). SW1 is controlled by DATA1. SW2 is controlled by DATA2.
S SLAVE ADDRESS S: Start A: Acknowledge P: Stop A DATA1 A DATA2 A P
Slave address
R/W bit Usually "0" (W: Master transmitter transmits to slave receiver) 1 0 0 1 0 0 X 0 Possible to select 20 pin High: 1, Low: 0
Rev.2.00 Sep 14, 2006 page 6 of 13
M52790SP/FP
Data Byte Format
M52790 FUNCTION TABLE
S SLAVE ADDRESS A DATA (D7 to D0) A DATA (DF to D8) A P
SLAVE ADDRESS
SLAVE ADDRESS A6 1 A5 0 A4 0 A3 1 A2 0 A1 0 A0 0/1 R/W 0
DATA1 (D7 to D0) CONT
DATA CONT D7 D6 AUDIO MODE1 D5 -- D4 Y/C AMP1 D3 V AMP1 D2 S/N D1 D0 SW1 CONT
VIDEO SW1 CONT
DATA S/N (S:1) D2 0 0 0 0 1 1 1 1 V-SW1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 V OUT1 T IN V 2 IN V 3 IN V 4 IN Y/C MIX T Y/C MIX 2 Y/C MIX 3 Y/C MIX 4 Y OUT1 Y IN Y IN Y IN Y IN Y IN Y 2 IN Y 3 IN Y 4 IN C OUT1 C IN C IN C IN C IN C IN C 2 IN C 3 IN C 4 IN OUT
AMP1 GAIN CONT
DATA D4 0 1 AMP YC AMP1 0 dB 6 dB DATA D3 0 1 AMP V AMP1 0 dB 6 dB
AUDIO MODE1 CONT
DATA D7 0 0 1 1 D6 0 1 0 1 MUTE R/R L/L NORMAL MODE
AUDIO SW1 CONT
MODE DATA D1 0 0 1 1 D0 0 1 0 1 MUTE MUTE MUTE MUTE MUTE OUT
Lch OUT 1 Rch OUT 1
R/R OUT
Lch OUT 1 Rch OUT 1
L/L OUT
Lch OUT 1 Rch OUT 1
NORMAL OUT
Lch OUT 1 Rch OUT 1
MUTE MUTE MUTE MUTE
Rch T IN Rch 2 IN Rch 3 IN Rch 4 IN
Rch T IN Rch 2 IN Rch 3 IN Rch 4 IN
Lch T IN Lch 2 IN Lch 3 IN Lch 4 IN
Lch T IN Lch 2 IN Lch 3 IN Lch 4 IN
Lch T IN Lch 2 IN Lch 3 IN Lch 4 IN
Rch T IN Rch 2 IN Rch 3 IN Rch 4 IN
Rev.2.00 Sep 14, 2006 page 7 of 13
M52790SP/FP DATA2 (DF to D8) CONT
DATA CONT DF DE DD -- DC Y/C AMP2 DB V AMP2 DA S/N D9 D8 AUDIO MODE2 SW2 CONT
VIDEO SW2 CONT
DATA S/N (S:1) DA 0 0 0 0 1 1 1 1 V-SW2 D9 0 0 1 1 0 0 1 1 D8 0 1 0 1 0 1 0 1 V OUT2 T IN V 2 IN V 3 IN V 4 IN Y/C MIX T Y/C MIX 2 Y/C MIX 3 Y/C MIX 4 Y OUT2 Y IN Y 2 IN Y 3 IN Y 4 IN Y IN Y 2 IN Y 3 IN Y 4 IN C OUT2 C IN C 2 IN C 3 IN C 4 IN C IN C 2 IN C 3 IN C 4 IN OUT
AMP2 GAIN CONT
DATA DC 0 1 AMP Y/C AMP2 0 dB 6 dB DATA DB 0 1 AMP V AMP2 0 dB 6 dB
AUDIO MODE2 CONT
DATA DF 0 0 1 1 DE 0 1 0 1 MODE MUTE R/R L/L NORMAL
AUDIO SW2 CONT
MODE DATA D9 0 0 1 1 D8 0 1 0 1 MUTE MUTE MUTE MUTE MUTE OUT
Lch OUT 2 Rch OUT 2
R/R OUT
Lch OUT 2 Rch OUT 2
L/L OUT
Lch OUT 2 Rch OUT 2
NORMAL OUT
Lch OUT 2 Rch OUT 2
MUTE MUTE MUTE MUTE
Rch T IN Rch 2 IN Rch 3 IN Rch 4 IN
Rch T IN Rch 2 IN Rch 3 IN Rch 4 IN
Lch T IN Lch 2 IN Lch 3 IN Lch 4 IN
Lch T IN Lch 2 IN Lch 3 IN Lch 4 IN
Lch T IN Lch 2 IN Lch 3 IN Lch 4 IN
Rch T IN Rch 2 IN Rch 3 IN Rch 4 IN
Rev.2.00 Sep 14, 2006 page 8 of 13
M52790SP/FP
Electrical Characteristics
(Ta = 25C, VCC = 9 V, unless otherwise noted)
Item Supply voltage Circuit current Video Voltage gain Symbol VCC ICC Min 4.7 -- -- -0.5 5.5 -0.5 Frequency characteristics F 5.5 -2.0 -2.0 -2.0 Dynamic Range D -2.0 4 2 4 Input impedance ZIC ZIV ZIY Crosstalk Audio Voltage gain Frequency characteristics Total harmonic distortion Dynamic Range Output DC offset voltage Input impedance Crosstalk I C Bus control signal Max. input high voltage Min. input low voltage Low level output voltage (SDA) High level input current Low level input current SCL clock frequency Time of bus must be free before a new transmission can start Hold time at start condition The low period of the clock The high period of the clock Step-up time for start condition
2
Typ -- 63 54 0 6 0 6 0 0 0 0 -- -- -- -- 20 -- -- -60 0 0 0 0.01 6.0 0 30 -90 -- -- -- -- -- -- --
Max 9.3 83 71 0.5 6.5 0.5 6.5 2.0 2.0 2.0 2.0 -- -- -- -- 26 -- -- -54 0.5 0.5 1 0.05 -- 20 38 -84 5.0 1.5 0.4 10 10 100 --
Unit V mA
Test Condition VCC = 9 V, Vin = 0 Vp-p, Rl = VCC = 5 V, Vin = 0 Vp-p, Rl = f = 100 kHz, 1 Vp-p (0 dB) (TV1OUT) f = 100 kHz, 1 Vp-p (6 dB) (TV1OUT) f = 100 kHz, 1 Vp-p (0 dB) (YV1OUT)
G
dB
dB
f = 100 kHz, 1 Vp-p (6 dB) (YV1OUT) f = 10 MHz/100 kHz, 1 Vp-p (0 dB) (TV1OUT) f = 10 MHz/100 kHz, 1 Vp-p (6 dB) (TV1OUT) f = 10 MHz/100 kHz, 1 Vp-p (0 dB) (YV1OUT)
Vp-p
2 14 -- -- -- -0.5 -0.5 -2.0 -- 5.5 -20 22 -- 3.0 0.0 0.0 -10 -10 0.0 4.7
k
f = 10 MHz/100 kHz, 1 Vp-p (6 dB) (YV1OUT) f = 100 kHz VCC = 9 V (0 dB) (TV1OUT) Maximum with VCC = 5 V (0 dB) (TV1OUT) distortion VCC = 9 V (0 dB) (YV1OUT) <1.0% VCC = 5 V (0 dB) (YV1OUT) (C, C2, C3, C4) Clamp in (T, V2, V3, V4) Clamp in (Y, Y2, Y3, Y4)
CT G F THD D VOFF Z1 CT VIH VIL VOL IIH IIL fSCL tBUF
dB dB dB % Vp-p mV k dB V
f = 1 MHz, 1 Vp-p TV1OUT (at V2 mode) f = 1 kHz, 1 Vp-p (VCC 9 V) (RTR1OUT) f = 1 kHz, 1 Vp-p (VCC 5 V) (RTR1OUT) f = 100 kHz/1 kHz, 1 Vp-p (RTR1OUT) f = 1 kHz, 2 Vp-p, at 400 Hz HPE + 30 kHz LPF (RTR1OUT) f = 1 kHz, Maximum with distortion < 0.5% (RTR1OUT) (MODE: RT, R2, R3, R4R1OUT) (RT, R2, R3, R4, LT, L2, L3, L4) 1 kHz, 1 Vp-p RTR1OUT (at R2 mode)
SDA = 3 mA A kHz s SDA, SCL = 4.5 V SDA, SCL = 0.4 V
tHD;STA tLOW tHIGH tSU;STA
4.0 4.7 4.0 4.7
-- -- -- --
-- -- -- --
Rev.2.00 Sep 14, 2006 page 9 of 13
M52790SP/FP
Electrical Characteristics (cont.)
(Ta = 25C, VCC = 9 V, unless otherwise noted)
Item Hold time DATA Setup time DATA Rise time of both SDA and SCL line Fall time of both SDA and SCL line Setup time for stop condition Symbol tHD;DAT tSU;DAT tR tF tSU;STO Min 5.0 250 -- -- 4.0 Typ -- -- -- -- -- Max -- -- 1000 300 -- s Unit ns Test Condition
I2C Bus Control Signal
SDA
tBUF tR tF tHD; STA
SCL
tSU; STO P S tLOW tHD; STA tHD; DAT tHIGH tSU; DAT tSU; STA Sr P
Rev.2.00 Sep 14, 2006 page 10 of 13
M52790SP/FP
Application Circuit Example
0.01 F 100 F
VCC
1
75 0.47 F
VCC VIDEO 2 IN Lch 2 IN C 2 IN Rch 2 IN Y 2 IN VIDEO 3 IN Lch 3 IN C 3 IN
TUNER IN 36 Lch T IN 35 C IN 34 Rch T IN 33 Y IN 32 V 1 OUT 31 Lch 1 OUT 30 C 1 OUT 29 Rch 1 OUT 28 Y 1 OUT 27 V 2 OUT 26 Lch 2 OUT 25 C 2 OUT 24 Rch 2 OUT 23 Y 2 OUT 22 BIAS 21
+
0.47 F 75
2 3 4
10 F
10 F 0.01 F 10 F
+
+ + +
TUNER IN
VIDEO 2 IN
75
+
0.01 F 10 F
0.47 F
Y/C Sepa.
5 6 7 8 9
+
75 75 0.47 F 0.47 F 10 F
75 75
+
+ + +
VIDEO 3 IN
OUT 1
+ +
75
75
0.01 F 10 F
10 Rch 3 IN 11 Y 3 IN 12 VIDEO 4 IN 13 Lch 4 IN 14 C 4 IN
75 75
+
75 75 0.47 F 0.47 F 10 F
+
75
VIDEO 4 IN
75 75
+
+ + +
0.01 F 10 F
75
OUT 2
+ +
75
15 Rch 4 IN 16 Y 4 IN 17 SCL
75 10 F
+
75 0.47 F
10 k 5V
220
I2C IN
CHIP SELECT 20 Slave address change (VCC/GND) GND 19
10 k 5V
220
18 SDA
Rev.2.00 Sep 14, 2006 page 11 of 13
+
+
M52790SP/FP
Note How To Use This IC
* * * * Input signal with sufficient low impedance to input terminal. The capacitance of output terminal as small as possible. Set the capacitance between VCC and GND near the pins if possible. Assign an area as large as possible for grounding.
Power-on Reset * The M52790 has an internal power-on reset function that sets each control register to "0" during IC power ON. * The power-on reset VTH has 2.5 V.
Rev.2.00 Sep 14, 2006 page 12 of 13
M52790SP/FP
Package Dimensions
JEITA Package Code P-SSOP36-8.4x15-0.80 RENESAS Code PRSP0036GA-B Previous Code 36P2R-D MASS[Typ.] 0.5g
36
19
HE
*1
E
F
1 Index mark
18
c
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
*2
D
A2 *3
A1
Reference Symbol
A
Dimension in Millimeters
e
y
bp
D E A2 A A1 bp c HE e y L
Detail F
Min Nom Max 14.8 15.0 15.2 8.2 8.4 8.6 2.05 2.35 0 0.1 0.2 0.3 0.35 0.45 0.18 0.2 0.25 0 8 11.63 11.93 12.23 0.65 0.8 0.95 0.10 0.3 0.5 0.7
Rev.2.00 Sep 14, 2006 page 13 of 13
L
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Keep safety first in your circuit designs!
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